(a) Fields of the Invention
The present invention relates to semiconductor devices including pads.
(b) Description of Related Art
With the aim of reducing chip size, various types of semiconductor device structures are proposed which each have a bonding pad arranged on an element formation region of an input/output (I/O) cell.
However, when the pad is formed on an element, impact load applied by wire bonding to the pad may cause damages to an interconnect or an interlayer insulating film immediately below the pad. In addition, the impact load may degrade operating characteristics of a diffusion element such as a transistor formed immediately below the pad.
For example, wire bonding employing gold ball bonding is conducted by the following process: while a chip is heated to 230 to 240° C. and a predetermined load is applied to a gold ball, ultrasonic wave is applied to break an oxide film on the surface of an aluminum pad, thereby forming an alloy of gold and aluminum between an aluminum intrinsic surface and a gold interface. By this process, energy of ultrasonic wave applied through the gold ball to the pad during the wire bonding generates stress at the interface between an interlayer insulating film and a metal below the pad, which in turn creates cracks in the interlayer insulating film made of SiO2 or the like. Also, it is known that by this process, the characteristics of a transistor (Vt, Gm, lifetime of a hot carrier, and the like) formed immediately below the pad are degraded (see, for example, Extended Abstracts (The 45th Spring Meeting, 1998), The Japan Society of Applied Physics and Related Societies, Vol. 3, p. 849).
Moreover, for a cantilever-type probe testing, which is a general approach of a probe testing, a needle of tungsten or the like is pressed against the pad. Thus, a large concentrated load is applied to a portion immediately below the pad, which may cause cracks into the interlayer insulating film.
In order to reduce such damages caused by bonding, probe testing, and the like, the structure as shown below (see, for example, U.S. Pat. No. 5,751,065) is disclosed.
FIG. 21 shows a cross-sectional structure of a semiconductor device according to a conventional example, and FIG. 22 shows a plan structure of a metal layer 215 in FIG. 21. Referring to FIGS. 21 and 22, dielectric layers 213 and 217 are formed over a substrate 201 having an active device 203 provided thereon, and a pad 219 is formed on the dielectric layer 217.
The patterned metal layer 215 is formed in a portion of the dielectric layer 217 located below the pad 219. The metal layer 215 formed immediately below the pad protects the active device from stress generated by a bonding process.